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Logic gate
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#	Item
241	Microsoft Word - fpga061s-mishchenko1.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-12-16 19:04:56 Digital electronics Electronic design And-inverter graph Field-programmable gate array Logic synthesis Static timing analysis Placement Logic optimization Propagation delay Electronic engineering Electronic design automation Formal methods
242	Fast Minimum-Register Retiming via Binary Maximum-Flow Alan Mishchenko Aaron Hurst Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-11-20 10:30:53 Formal methods Electronics Retiming Electronic design automation Maximum flow problem Flow network Digital electronics Ford–Fulkerson algorithm Logic gate Network flow Electronic engineering Mathematics
243	SynaptiCAD Big Feature List SynaptiCAD was founded in 1992 to provide affordable high quality timing diagram editing tools. Since that time we have expanded our product line to include: VHDL & Verilog test bench generati Add to Reading List Source URL: www.syncad.com Language: English - Date: 2011-04-06 10:25:45 Verilog VHDL Waveform viewer Logic analyzer Field-programmable gate array Jitter Aldec Phase-locked loop Static timing analysis Electronic engineering Electronics Hardware description languages
244	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 3, JUNE[removed]Transactions Briefs__________________________________________________________________ Board-Level Multiterminal Net Assignm Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2003-07-31 11:09:07 Logic in computer science NP-complete problems Electronic design automation Formal methods Boolean algebra Boolean satisfiability problem Field-programmable gate array MOS Technology SID Hardware emulation Theoretical computer science Electronic engineering Applied mathematics
245	LUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations Tsutomu Sasao 1 and Alan Mishchenko[removed]Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka[removed], Japan Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-07-09 02:20:06 Boolean algebra Diagrams Field-programmable gate array Binary decision diagram Lookup table Xilinx Multiplexer Artificial neuron Function Computing Mathematics Electronic engineering
246	Global Delay Optimization using Structural Choices Abstract This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mappe Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-09-11 21:52:58 Digital electronics Electrical circuits Diagrams And-inverter graph Field-programmable gate array Static timing analysis Propagation delay Logic synthesis Retiming Electronic engineering Electronic design automation Formal methods
247	Generalized Universal Circuits for Secure Evaluation of Private Functions with Application to Data Classification Ahmad-Reza Sadeghi and Thomas Schneider? Horst G¨ ortz Institute for IT-Security, Ruhr-University Bochum, Add to Reading List Source URL: eprint.iacr.org Language: English - Date: 2008-12-22 15:22:51 Logic gates Computational complexity theory Circuit complexity Boolean circuit Logic in computer science Adder ACC0 OR gate Theoretical computer science Applied mathematics Digital circuits
248	VLSI DESIGN 1996, Vol. 4, No. 2, pp. i-ii (C[removed]Reprints available directly from the publisher Add to Reading List Source URL: downloads.hindawi.com Language: English - Date: 2014-05-11 09:05:38 Logic design Field-programmable gate array Hindawi Publishing Corporation CPU design Logic simulation Parallel computing Application-specific integrated circuit Digital electronics Simulation Electronic engineering Electronic design automation Integrated circuits
249	Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Jie-Hong Jiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-05-01 15:17:53 Digital electronics Electronic design And-inverter graph Retiming Logic synthesis Algorithm Field-programmable gate array Logic gate Parallel computing Electronic engineering Electronic design automation Formal methods
250	An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton Department of EECS University of California, Berkeley {alanmi, satrajit, brayton}@eecs.berkeley.edu Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-07-16 00:13:15 Integrated circuits Electronic design Placement Logic synthesis Field-programmable gate array Jason Cong Complex programmable logic device Application-specific integrated circuit Electronic engineering Electronics Electronic design automation

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